1. Field of the Invention
The present invention relates to status timers for detecting abnormal behavior in real time processors or microcontrollers and, in particular, to apparatus for improving the reliability of such timers.
2. Description of Related Art
Processors commonly used for real time controller applications, such as the Intel 8096, Intel 80C252, Siemens 80515, and NEC 7811, employ an apparatus known as a watchdog timer. The watchdog timer is a status timer which must be reset by the processor within a selected time period. If the processor does not reset the watchdog timer, abnormal operation of the processor is assumed. In this case, the watchdog timer generates a reset signal for its host processor.
The selected period within which the processor must reset the watchdog timer is stored in registers or latches in prior art systems in response to program control of the host processor. The contents of the register or latch holding the code indicating the selected time interval is compared continuously with the output of a counter. When the counter reaches the threshold value, a reset signal is generated. Problems arise in maintaining correct operation of the watchdog timer during or after an electrostatic discharge (ESD), power glitches, or errant software. Because the code which indicates the interval within which the watchdog timer must be reset, is stored in registers or latches, ESD and power glitches can cause changes in the preselected code, interfering with normal operation of the watchdog timer. Also, because those storage elements are accessible by software control of the processor, errant software can alter the preselected code as well.
Because microcontrollers or processors used for real time control applications are often employed in harsh environments, a need arises for watchdog timers that are immune from ESD, power glitches and errant software.